A basic operational function of systems involving digital modules has to do with transfer of data between various of the digital modules. Problems arise in regard to the accounting for and making sure that a specified amount of data has been transferred and has been transferred on a reliable basis with integrity.
As seen in FIG. 2A, there is indicated a block diagram of a data transfer system whereby data from a host processor 4 may be transferred to a channel interface module (CIM) 8.sub.c and then transferred to a device interface module (DIM) 8.sub.d from which the data can then be moved to one or more peripheral units such as the shown disk drive units 70. FIG. 2B indicates the DIM 8.sub.d with a protocol bus 6 connecting a buffer 24.sub.d to a Protocol Controller 80 with an integrity circuit 81 (Ic).
Then, in a more detailed version in FIG. 2C, a system can be provided wherein multiple numbers of host processors, 4a . . . 4d, are connected to multiple numbers of channel interface modules (CIM)each of which are connected to dual system busses 6.sub.a and 6.sub.b which then can connect to multiple numbers of device interface modules (DIMs) 8.sub.d each of which provides four ports as input/output ports to a plurality of peripheral units such as the disk drive units 70 (70.sub.a . . . 70.sub.d).
As seen in FIG. 3A, a block of data composed of "X" bytes will have a header portion which will provide the address and destination with commands and include information as to the size of the block. After the header, there is present the main bulk of the data which is followed by a signature portion designated as the error detection code (EDC) signature. This has been provided to the block of data in order to characterize a value which represents the value of the data being transmitted in the main block.
Subsequently, as seen in FIG. 3B, there may be data block transfers of a different volume or size as shown by the block designated "Y" bytes. Here again the header will provide the address destination, commands and other pertinent data after which the main body holds the data to be transferred followed by the EDC (error detection code) signature which characterizes the data being transferred.
When a block of data such as that of "X" bytes or "Y" bytes is being transferred, it is necessary not only that some means be provided to recognize the block size and to insure the integrity of the data transfer but that the entire specified number of bytes in each block and the number of specified blocks, has been transferred. As seen in FIG. 4, there is shown an example of two different block sizes which are to be transmitted between a sending and a receiving digital module, the first block size being of 180 bytes and having header and EDC signature. This is followed by a larger block size of 512 bytes which also has its own personal header and EDC signature.
The presently described system operates to insure that there will be no delay in the data transfer operation even though blocks of different sizes are being transferred and additionally, that the different block sizes will concurrently and on-the-fly be checked for integrity without any delay to the data transfer operation and that the specified proper number of blocks be transferred.
As seen in FIGS. 2B, 2C, the device interface module 8.sub.d (DIM) which is used to carry data to peripheral units such as a disk drive unit 70, will be seen to have certain functioning modules which enhance the transfer of data to the peripherals while at the same time providing for reliability in the data transfer operation by checking the integrity via I.sub.c, 81, FIG. 2B, of the data being transferred. As seen in FIGS. 2B, 2C data which has been passed down from the channel interface module 8.sub.c (CIM) and which temporarily resides in the memory buffer 24.sub.d, will then be passed on bus 6 to SCSI Protocol Controller SPC 80, which will provide the management for transferring the data on bus 78 to a selected group of disk drives 70. The drives 70 may represent a multiple number of peripheral units which can receive blocks of data or send blocks of data.
As seen in FIG. 2B, the bus 6 between the memory buffer 24.sub.d and the protocol controller SPC 80 is also connected to an integrity circuit I.sub.c 81. The integrity circuit 81 functions on-the-fly in order to check the integrity of the data being transferred. A control processor 10.sub.d provides initiation signals to the integrity circuit 81 so that it may provide its error checking function.
As illustrated in FIGS. 3A, 3B, blocks of data to be transferred can occur in different block sizes. FIG. 4 illustrates where each header of a block contains information as to the size of the block by denoting the number of bytes involved in the block. Then, after the pertinent data in the block is transmitted, the final portion of each block is seen to have an Error Detection Code (EDC) signature. This signature involves a Hexadecimal Code of, for example, nine bytes (36 bits) of which the first byte is a parity value.
Thus, in addition to checking the integrity of the data being transferred, there is also the problem of making sure that the entire block of data of, for example, 180 bytes or, for example, 512 bytes, has been transferred from one digital module to the other destined receiving digital module. The data feeder control F.sub.0, FIG. 1A, (DFC) of the presently described system performs the function of making sure that only the valid blocks of data available in the memory buffer 24.sub.d are transferred with integrity to the receiving module even though the host processor 4 has commanded a specific protocol-controller SPC 80 to transfer a larger total of "B" data blocks in total. In the case of a EDC error or a parity error, or in the case of all the bytes having been properly transferred from a sending module to the receiving module, then in that case, there is no more data available in the memory buffer for transfer. In each of these cases, the data feeder control (DFC) system will force a control logic unit so as to deny any further grants of protocol bus 6 to the protocol controller SPC 80.